Recently, SUSTech School of Microelectronics undergraduates Ziyi Guan and Kai Li made great progress in the field of artificial intelligence and edge computing. Their results, entitled “Video-based Fall Detection Network by Spatio-temporal Joint-point Model on Edge Devices” and “A Reconfigurable Multiple-Precision Floating-Point MAC for High-Performance Computing” have been accepted by Design, Automation & Test in Europe Conference (DATE 2021), respectively.

This is the first time that SUSTech undergraduate has published a paper in the DATE conference as the first author.

DATE (Design, Automation & Test in Europe), DAC (Design Automation Conference) and ICCAD (International Conference on Computer-Aided Design) are the three top conferences in the EDA field and also the top international academic conferences on Computer System and High-Performance Computing recommended by China Computer Society (CCF).

Both articles were mainly completed by undergraduates of SUSTech. Ziyi Guan is the first author of the algorithm design paper. His research has made a breakthrough in video understanding systems on edge devices, which improves the accuracy and stability of the elderly fall detection system. Tripping or falling is among the top threats in elderly healthcare, so the development of automatic fall detection systems are of considerable significance.

Fig. 1. The proposed video fall detection network based on the Spatio-temporal joint-point model.

The first author of the paper on chip design is Wei Mao, a teacher from the School of Microelectronics, and the second author is Kai Li, an undergraduate of the School of Microelectronics. This paper proposes a multiple-precision floating-point processing unit for high-performance computing, which can reconfigure architecture based on the efficient SIMD architecture, and reduce the hardware cost and instruction interaction process, thus improving operation speed and data processing ability. Such proposed processing unit can be widely used in scientific computation and machine learning training to solve the bottleneck issue during multiple-precision data processing.

Fig. 2. Architecture of 10-input PEs based on the reconfigurable adder tree.

Related works are under the supervision of Prof. Hao Yu’s group.