The team led by Associate Professor Yury Illarionov from the Department of Materials Science and Engineering at Southern University of Science and Technology (SUSTech) conducted in-depth research on dual-gate ITO/HfO₂ field-effect transistor systems. Through systematic reliability analysis (including universal hysteresis mapping, bias temperature instability testing, and TCAD simulations), they revealed for the first time that full coverage of the amorphous oxide channel by the top-gate metal electrode is the key to long-term device stability. The related results were published in the academic journal ACS Nano under the title “Long-Term Operational Stability of Dual-Gated ITO/HfO₂ Field-Effect Transistors via Full Top-Gate Coverage: A Comprehensive Bias-Stress Mapping.”

Figure 1. ITO/HfO₂ Transistor Structure and Fundamental Physical Mechanisms

Indium tin oxide (ITO) is a promising thin-film semiconductor material suitable for transistors in advanced chips, such as 3D integration. However, the challenge in fabricating ITO transistors that ensure long-term stable operation lies in constructing high-quality gate stacks while maintaining the stability of the top gate to avoid negative threshold voltage drift. In this study, imaging with scanning electron microscopy (SEM) and transmission electron microscopy (TEM) confirmed that the top gate metal fully covers the 4nm-thick ITO channel. Combined with a symmetric sandwich structure of 15nm HfO₂ gate dielectrics above and below, this can physically block the penetration of H⁺ and oxygen into the top oxide layer. Both the device’s back gate and top gate can be precisely modulated to a zero-bias turn-on state by applying opposite gate biases, demonstrating high stability with ultra-low hysteresis and drift. Further analysis showed that the upper defect band of HfO₂ is above the conduction band minimum of ITO, making it difficult for defect states to be reached by the Fermi level of ITO, thereby preventing charge trapping. In the MoS₂ system, the HfO₂ defect band is close to the Fermi level of MoS₂, significantly enhancing the hysteresis effect.

Figure 2. Impact of Top-Gate Sweep Range Optimization on Hysteresis Effect and TCAD Energy Band Simulation

To verify that the primary cause of stability is the relative position of the HfO₂ defect band and the ITO energy level, the research team used a self-developed long-term hysteresis dynamic analysis technique to systematically scan 3,000 current points on the transfer curve of the transistor, constructing a mapping relationship between hysteresis width (ΔV_H) and scan frequency (1/t_sw), ultimately obtaining a universal hysteresis function. In addition, the team employed Minimos-NT to establish a high-precision TCAD reliability model. By introducing a band alignment framework and setting key parameters such as trap density, effective mass, dielectric constant, defect bandwidth, and capture cross-section, they qualitatively reproduced the measured transfer characteristics, threshold voltage modulation, and control of hysteresis width. Under zero-bias off-state conditions and with back-gate and top-gate modulation, the device exhibited hysteresis as low as 25 mV and 60 mV, respectively, when the total sweep duration was 6.6 ks (derived from the upper hysteresis function). Based on the above testing method, the team treated the back-gate HfO₂ defects as fixed charges and focused on optimizing the effect of the top-gate sweep range (V_TGmin/V_TGmax). The results show that when V_TGmin is more negative, hysteresis is mainly determined by the lower defect band of HfO₂; the Fermi level decreases, and hole capture leads to significant hysteresis. However, when V_TGmin approaches 0, the Fermi level rises, most of the lower defect band moves into the lower inactive region, the defects remain neutral, and only the upper defect band participates, which is above the ITO conduction band, thereby reducing the hysteresis width. On the other hand, the hysteresis width increases with an increase in V_TGmax; as the Fermi level further rises, more trailing states in the upper defect band participate in electron capture. TCAD simulations illustrate the changes in hysteresis width, confirming that quantitative band engineering analysis is the core method for studying hysteresis in ITO/HfO₂ transistors.

Figure 3. Long-term stability of ITO/HfO₂ transistors under static bias stress

On this basis, the research team conducted positive bias temperature instability (PBTI) experiments on dual-gate ITO transistors, systematically evaluating the long-term reliability by optimizing the testing method (10 ks stabilization and zero-bias off-state conditions). The results show that the positive threshold voltage shift caused by PBTI is tens of millivolts, with no negative shift observed at room temperature, confirming the clockwise hysteresis dynamics. The time-resolved current curves demonstrate drift decay phenomena at both back gate and top gate under high gate voltage stress (3V) and prolonged stress duration (30 ks). The top gate also exhibits an additional positive charge contribution, which can self-heal under long-term on-state conditions. This phenomenon may originate from the injection of fixed positive charges at the back gate that compensate for electron trapping, slow drift of oxygen vacancies, and H⁺ impurity migration, rather than defects caused by incomplete coverage. Therefore, compared with previous work (where severe PBTI-induced negative threshold voltage shifts were observed at the top gate at room temperature), the device was effectively suppressed even under continued stress of at least 10 ks, confirming the importance of full metal coverage on the top oxide.

Figure 4. Reliability limits of ITO/HfO₂ transistors in high-temperature environments

This dual-gate ITO transistor maintains high stability at elevated temperatures: within the temperature range of 25°C to 105°C, the hysteresis width of the back gate is always kept within tens of millivolts, with only slight counterclockwise hysteresis observed during low-frequency sweeps at 105°C, indicating a low concentration of mobile charges in the back-gate HfO₂. The top gate is more sensitive to temperature changes. Counterclockwise hysteresis is fully activated during a low-frequency sweep at 105°C, accompanied by a negative shift of the threshold voltage. However, some devices show a negative shift of less than 50 mV under 85°C/10 ks stress conditions. The low charge migration characteristic of the top gate is mainly due to its slow oxygen vacancies, rather than H⁺ ions induced by the process.

Figure 5. Reliability performance comparison

Compared with MoS₂-based transistors prepared by advanced processes, including IMEC and Intel, the ITO/HfO₂ devices in this study show significant advantages in zero-bias turn-off and hysteresis. By normalizing the equivalent oxide thickness (EOT), the hysteresis width was consistently lower than that of all the comparison devices. The core advantage is that the positive threshold voltage drift is small after applying 30ks stress at room temperature, and the negative drift activated above 85°C is still lower than the room temperature data of other studies. Full top gate coverage can effectively block pollutants, and the ITO/HfO₂ defect band level matching is better than that of MoS₂-based systems, which fundamentally reduces the activity of defect capture. In addition, the research team followed the standardized hysteresis analysis framework proposed in 2D material transistors, offering a new paradigm for evaluating the reliability of amorphous oxide devices in the post-Moore era.

Jianming HUANG, a 2024-entry PhD candidate in the Department of Materials Science and Engineering at SUSTech, is the first author of the paper, and Professors Tania Roy of Duke University and Yury Illarionov of SUSTech are the co-corresponding authors of the paper. SUSTech is the first affiliated institution.

Paper link: https://pubs.acs.org/doi/full/10.1021/acsnano.5c17437